Electronic firing delay device, demolition

ABSTRACT

An electronic firing delay device comprising an oscillator, digital frequency divider, gating device, electronic switch, capacitor bank, electrical squib and power supply. In operation, the oscillator output is divided and the desired time delay is selected by a switch. The output of the divider closes the SCR switch, discharging the capacitor bank through the squib, forcing out the firing pin.

Unifie Sites Hoyt et'al. Dec. 10, 1974 [54] ELECTRONIC FIRING DELAY DEVICE, 3,646,371 2/1972 Flad 102/702 R EMO T O 3,657,571 4/1972 Martin et al. 102/702 R Inventors: John D. Hoyt, Oxon Hill; John J.

Pennella, Bryans Rd both of Md.

Filed: Aug. 30, 1973 Appl. N0.: 393,096

Assignee:

Primary ExaminerBenjamin A. Borchelt Assistant ExaminerC. T. Jordan 5 7 ABSTRACT An electronic firing delay device comprising an oscillator, digital frequency divider, gating device, electronic switch, capacitor bank, electrical squib and 52 US. Cl 102/70.2 R Power pp y- In Operation, the Oscillator Output is 51] 1m. 01. F42C 11/06 vided and the desired time delay is Selected y a 58 Field of Search 102/702 R, 82; 317/80 switch The Output of the divider closes the SCR switch, discharging the capacitor bank through the 5 References Cited squib, forcing out the firing pin.

A N UNITED STATES P TE TS 5 Claims, 2 Drawing Figures 3,067,684 12/1962 Eukeretal. 102/702 R DELAY OSCILLATOR FREQUENCY LOG'C SELECTION DlVIDER GATES SWITCH [IO {I2 I4 16 SHEET 2 BF 2 PAIENIEL nu: 1 mm ELECTRONIC FIRING DELAY DEVICE, DEMOLITION I BACKGROUND OF THE INVENTION The present invention relates generally to fuses, primers and igniting devices and more specifically to electronic firing delay circuits. Prior mechanical time delay devices are expensive to produce and inherently inaccurate in operation. Typically, inaccuracies of up to 4 percent of the delay time are not uncommone. Their complexity and lack of reliability have been a continuing problem. For example, a delay inaccuracy of 4 percent for a firing delay of 12 hours amounts to a one half hour deviation in the detonation time. Similarly, a firing delay period of 72 hours leads to a 3 hour deviation in detonation time. The inherent limitations involved with this amount of delay are clear. First, they cause a potential hazard to those persons who handle these devices because of their inaccuracy. Second, a great amount of time is wasted in determining that these devices have failed to detonate and are not still within their inaccuracy range, especially for long delay times. Also, the errancy of the prior mechanical firing delay devices has caused more reliance on expensive safety disarming devices which must be incorporated therein.

Other disadvantages of the mechanical firing delay devices such as the fact that they fail to provide any practical means for testing their operation before use to determine if their working parts are operational, their high cost of production, their size limitations, etc., have led to the development of the present invention.

SUMMARY OF THE INVENTION The present invention overcomes the disadvantages and limitations of the prior art by providing an electronic firing delay circuit. The firing circuit comprises an oscillator, a digital frequency divider, gating logic, a delay selection switch, a pulse circuit, an indicator, and a squib. The oscillator provides a pulse signal which is divided down by a divider and logic gates. The delay selection switch conducts a signal at the end of the period selected to a pulse circuit which produces a pulse to either indicate proper operation via the indicator or fire the squib to detonate the explosive.

It is therefore the object of the present invention to provide an inexpensive, simple, and reliable electronic firing delay circuit.

It is also an object of the invention to provide a firing delay circuit having a high degree of accuracy.

It is a further object of the present invention to provide a firing delay circuit which can be operated in a safe manner.

Another object of the invention is to provide a firing delay circuit which can be easily checked for proper operation.

Another object of the invention is to provide a firing delay circuit which is compact.

Other objects, advantages and novel features of the invention will become apparent from the following description of the invention when considered in conjunction with the accompanying drawings wherein:

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the preferred embodiment.

FIG. 2 is a circuit diagram of the preferred embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a block diagram of the electronic firing delay circuit comprising the present invention. Oscillator 1,0 constitutes the basic time reference for the device. It producesa pulse output which is divided down by powers of two by the frequency divider 12. Logic gates 14 and delay selection switch 16 select the desired delay produced by the frequency divider l2 and conduct its output signal to pulse circuit 18 which produces a pulse to either light the indicator 22 or fire squib 24 to actuate a firing pin.

FIG. 2 is a circuit diagram of the electronic firing delay device. Power is supplied by a battery 26 which can range from a 3 to 9 volt supply. Either of the two switches 28 or 30 is capable of applying power to the circuit. Switch 28 is an arming switch that can be set by pulling a cotter pin. Switch 30 is used exclusively for self testing of the circuits electronic parts.

The oscillator 10 comprises a single chip array of four NAND gates having two inputs each. This is distributed by RCA as a CD40l lAE complementary/metal-oxide semiconductor (c/mos). In fact, all the active components of the circuit rely on c/mos technology which have the advantages of being compact, relatively inexpensive and requiring very little power. Three of the NAND gates of oscillator 10 are connected in series and biased by resistors R R and R to form an inverting amplifier. The frequency of the oscillator is determined by capacitors C C and C resistor R and the quartz crystal. This oscillator is extremely stable and has been found to drift less than $0.2 percent over a voltage range of 3 to 9 volts and a temperature range of 40C to +C. As a result, the timing circuit is accurate within 0.4 percent of its total time interval which is at least a magnitude greater than that obtainable in the prior mechanical devices.

The output signal produced by oscillator 10 is subsequently fed to a frequency divider 12. When power is applied to the circuit via either switch 28 or 30, the series RC circuit comprising R and C resets the frequency divider to its zero state. The properties of the two series connected RCA CD4020AE ripple through counters requires that the RC time constant of R and C be approximately equal to 0.005 seconds. The ripple through counters (connected in series) are capable of dividing down the output frequency of oscillator 10 up to (/2) times.

The logic gates 14 are composed of two CD401 lAE chips connected in the manner shown to give delays ranging from 30 seconds to 12 hours for an oscillator frequency of 4649 Hz. Delay selection switch 16 selects the desired delay for conduction to silicon controlled rectifier (SCR) 21. At the end of the selected delay period an output signal is produced which fires the SCR 21 to do either of two things. If switch 20 is in position 1 the light emitting diode (LED) 22 will light up indicating the proper operation of the circuit. R is used to limit the current through LED 22. Position 2, of course, is in the off position. If the switch is in any of the positions 3 through 11, the capacitor bank (C which is part of pulse circuit 18 will discharge through squib 24 provided switch 25 is open (armed). Resistor R, is used to limit charging currents into capacitor C and to also prevent C from rapidly discharging through LED 22 when switch 20 is in the test position 1. The circuit is shown as positively grounded to its case to prevent RF energy from firing the squib.

The advantages of the present device are clear. The use of c/mos semiconductor devices has led to a current drain of less than 2.4 ma at 9 volts. When the LED is on for testing, the current drain increases to 50 ma. In addition, the circuit will operate with a supply voltage of anywhere from 3 to volts. The cost of the production of this device has been found to be one-third of the cost' of the prior devices. The present device has at least 10 times greater accuracy over the prior mechanical devices while requiring less space. And finally, ithas a self test feature not available in the prior devices to quickly and easily determine reliability.

Obviously many modifications and variations of the present invention are possible in light of the above teachings. For example, use of any well known oscillator configuration such as unijunction, RC-phase shift, or a stable multivibrator could be made. Also, an inductor could be used in place of the crystal. This would perhaps reduce the cost of production but it would be at the expense of accuracy. Similarly, the frequency divider 12 and logic gates 14 could be replaced by a different logic family such as TTL, DTL, RTL, RDL, PMOS, etc. This however, may increase both the cost and the power supply requirements. In addition, any type of firing device could be used in place of the squib 24 such as an electric blasting cap. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.

We claim:

1. An electronic firing delay circuit for firing an explosive igniting device comprising:

means for producing a periodic signal having a predetermined frequency;

means for dividing the frequency of said periodic signal to produce a plurality of pulses on a plurality of channels each having a different frequency and each initially delayed by a single cycle of said different frequency;

means for selecting one of said plurality of channels;

switching means for completing a circuit loop so as to cause a capacitor in said circuit loop to discharge through said explosive igniting device causing said device to fire said explosive upon detecting the presence of one of said pulses on said selected channel.

2. The circuit of claim 1 wherein said capacitor is discharged through an indicator upon said detection of one of said pulses from said selected channel for indicating proper operation of said circuit.

3. The circuit of claim 1 wherein said means for selecting comprises:

eight dual input NAND gates; and,

a delay selection switch connected to said means for dividing and said NAND gates. 4. The circuit of claim 2 wherein said means for selecting comprises:

eight dual input NAND gates; and,

a delay selection switch connected to said means for dividing and said NAND gates.

5. The circuit of claim 1 wherein said switching means comprises:

semiconductor switching means connected to said means for selecting for completing said circuit loop upon the occurance of a pulse from said selected channel; and

additional switching means for selecting a conduction path of said capacitor through said igniting device to ignite said explosive.

l l l 

1. An electronic firing delay circuit for firing an explosive igniting device comprising: means for producing a periodic signal having a predetermined frequency; means for dividing the frequency of said periodic signal to produce a plurality of pulses on a plurality of channels each having a different frequency and each initially delayed by a single cycle of said different frequency; means for selecting one of said plurality of channels; switching means for completing a circuit loop so as to cause a capacitor in said circuit loop to discharge through said explosive igniting device causing said device to fire said explosive upon detecting the presence of one of said pulses on said selected channel.
 2. The circuit of claim 1 wherein said capacitor is discharged through an indicator upon said detection of one of said pulses from said selected channel for indicating proper operation of said circuit.
 3. The circuit of claim 1 wherein said means for selecting comprises: eight dual input NAND gates; and, a delay selection switch connected to said means for dividing and said NAND gates.
 4. The circuit of claim 2 wherein said means for selecting comprises: eight dual input NAND gates; and, a delay selection switch connected to said means for dividing and said NAND gates.
 5. The circuit of claim 1 wherein said switching means comprises: semiconductor switching means connected to said means for selecting for completing said circuit loop upon the occurance of a pulse from said selected channel; and additional switching means for selecting a conduction path of said capacitor through said igniting device to ignite said explosive. 